In the wave of pursuing higher performance, smaller size, and lower power consumption in the semiconductor industry, 3D integration technology has become a key path driving Moore's Law forward. Among numerous 3D packaging solutions, several mainstream advanced packaging technologies have emerged based on different integration methods and process sequences. With their unique structures and processes, they jointly support the grand blueprint of modern heterogeneous computing.

PoP: Package on Package Assembly

One of the simpler solutions to achieve 3D integration is to stack the already packaged chips. The technical name of such solutions usually includes "PoP" (i.e. "Package Stack"). A typical application scenario of this technology is stacking DRAM chips above logic chips, which is included in TSMC's InFO packaging technology.

CoW: Chip on Wafer Assembly/Wafer Level Chip Integration

One of the early solutions to achieve chip interconnection in packaging was to use wafers as carriers and fabricate rewiring layers (RDL) on them. TSMC branded this technology as "CoW" (wafer level chip integration). Here are two typical assembly process schemes:

The process of the first approach is to first fabricate a rewiring layer (RDL) on the carrier wafer, and then place the pre cut chips (with solder bumps facing downwards) on the carrier; Subsequently, the chip is encapsulated to form a "reconstructed wafer"; Afterwards, the carrier wafer is removed, solder balls are made, and finally the reconstructed wafer is singulated to obtain an independent package.

The process of another solution is different: first invert the chip onto the carrier wafer, and then perform plastic sealing; After removing the carrier wafer, fabricate a rewiring layer and solder balls; Finally, the reconstructed wafer is cut and packaged.

Intel's Foveros process is another variant of this technology, mainly used to achieve face-to-face bonding of two chips (or one chip with an active intermediate layer). Among them, the chip below needs to be placed facing upwards and connected to the substrate through silicon via holes (TSV).

Adding Interposers

The solution introduced earlier only achieves signal routing to solder balls through the rewiring layer (RDL). If an intermediate layer is added in the packaging, it can further enhance the flexibility of wiring. TSMC's CoWoS (wafer level system integration packaging) is one of the most well-known cases, which can be divided into three variants based on the type of intermediate layer:

CoWoS-S: using a silicon intermediate layer;

CoWoS-R: using organic materials to make rewiring layers (without independent intermediate layers, replacing the intermediate layer function with organic RDL);

CoWoS-L: uses a small chip as the "wiring carrier" - its structure is similar to a silicon bridge, but it also has additional vias leading to the substrate, which can be directly connected to the substrate.

Summary:

The evolution of advanced packaging clearly demonstrates a system level integration path from two-dimensional to three-dimensional, from single to heterogeneous, from simple package stacking (PoP) to wafer based chip integration (CoW), and then to CoWoS technology that introduces intermediate layers to maximize routing potential. These technologies not only break through the physical limitations of traditional packaging, but also provide unlimited possibilities for future computing power through flexible chip combinations. They together constitute the next frontier of the semiconductor industry, heralding a new era of electronic system performance and integration.